In the field of semiconductor technology, the electrostatic discharge (ESD) phenomenon poses a major threat to the reliability of an integrated circuit (IC) device. With the decrease in the feature size of semiconductor technology nodes, the design of ESD protection has become a more difficult and more challenging task in nanoscale CMOS technology.
Silicon-controlled rectifier (SCR) devices exhibit strong ESD robustness and strong current discharge capacity per unit area. SCR devices are widely used as on-chip structures for electrostatic discharge (ESD) protection. When integrated on-chip in a low-operating power source IC device, the high triggering voltage of an SCR device faces limitations in the range of applications. Therefore, some advanced techniques, such as Zener diode triggered SCR (alternatively referred to as Zener-triggered SCR) devices have been proposed to enhance the ESD efficiency. However, conventional Zener-triggered SCR devices consume a large silicon real estate. Conventional SCR devices also face the problems of lower current discharge capacity per unit area.
FIG. 1A is a cross-sectional view of a conventional Zener-triggered SCR device. FIG. 1B is a top plan view of the Zener-triggered SCR device of FIG. 1A. FIG. 1C is a schematic of a Zener-triggered SCR device that can be applied to the present invention. The Zener-triggered SCR device includes a SCR device and an auxiliary Zener diode integrated in the SCR device to speed up turn-on time of the SCR device. The Zener diode is disposed between a base of a PNP transistor and a base of an NPN transistor. The Zener diode is formed of an N+ implanted region and a P+ implanted region embedded within the SCR device. When an ESD event occurs at the anode of the SCR device, the Zener diode turns on first, causing a current flowing through the P-well of the SCR device, and ultimately turning on the SCR device through the voltage drop in the resistance of the P-well.
Comparing with conventional SCR devices, Zener-triggered SCR devices have an additional N+ implanted region in the junction region between the N-well and the P-well, and an additional P+ implanted region in the P-well. The P+ implanted region is adjacent to the N+ implanted region and forms together with the N+ implanted region an integrated Zener diode. The additional P+ implanted region and the additional N+ implanted region increase the silicon surface area, while reducing the current discharge capacity per unit area of the SCR device.
Thus, there is a need to provide a novel semiconductor device structure to reduce the surface area of the semiconductor substrate.